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CoreU1PHY – UTOPIA Level 1 PHY Interface
User Interface
The user interface can connect directly to Actel's
CoreATMBUF3 cell buffer, an intellectual property core
that provides buffering for up to three 54-byte ATM cells
in each direction ( Figure 1 on page 1 ). Alternatively, the
designer may choose to connect his/her own cell buffer
or user logic function directly to the user interface. The
signals associated with the user interface are
summarized in Table 3 .
Table 3 ? User Interface Signals
signals and data for the read interface are associated
with the u1_rx_clk.
Each interface is controlled from the user logic by the
w_avail and r_avail signals, respectively.
When the cell buffer or user logic is ready to receive or
send a cell on either interface, the user must assert
x_avail high. In turn, this will cause the CoreU1PHY to
assert u1_x_clav to the link-layer device.
Write Interface (ingress)
Signal
Type Description
Whenever the link-layer asserts u1_tx_en low, the
w_phy_act signal is asserted high to indicate that the
reset
xlate
w_avail
w_phy_act
w_enable
w_adr
w_data
r_avail
r_buf_en
r_adr
r_data
In
In
In
Out
Out
Out
Out
In
Out
Out
In
Active high – resets all registers
53 / 54-byte cell size control
Active high – user ready to receive
Active high physical selected
Active high data enable
5-bit word count
16-bit data bus
Active high – user ready to send
Active high read enable
5-bit word count
16-bit data bus
ingress user interface is active. The w_enable signal will
remain low until the link-layer begins to transfer a cell.
Since the CoreU1PHY translates from 8-bit data at the
UTOPIA interface to 16-bit data at the user interface,
w_enable is asserted for one clock cycle while a data
word is valid. W_adr is incremented on the next rising-
edge of u1_tx_clk, and then w_enable is de-asserted for
one clock cycle (except during insertion of the UDF2
byte, as shown in Figure 9 ). W_adr increments from 00 to
1B hex (27 words).
U1_tx_clk
U1_tx_clav
U1_tx_en
When reset is asserted high, all registers in the
CoreU1PHY are cleared. They will remain in this state as
U1_tx_soc
U1_tx_data
XX
H1
H2
H3
H4
H5
P1
P2
P3
long as reset is asserted.
If the xlate input is low, the CoreU1PHY will transfer data
w_phy_act
w_enable
to/from the link-layer device as 53-byte ATM cells. On
ingress (TX), the CoreU1PHY will duplicate the fifth byte
w_adr
00
01
02
03
of the ATM header and insert it as the sixth byte (UDF2)
w_data
XX
H1H2 XX H3H4 H5H5 XX
P1P2
in order to create a standard 54-byte ATM cell on the
user "write" interface. Conversely, the CoreU1PHY will
accept a standard 54-byte cell at the user "read"
interface and drop the sixth byte during transfer to the
egress (RX) interface. If xlate is high, no translation is
performed; 54-byte cells are transferred on all interfaces.
The user interface is divided into write (TX) and read (RX)
interfaces. The control signals and data for the write
interface are associated with the u1_tx_clk, while control
Figure 9 ? Write Interface Cell Transfer
If the address resets to 00 hex before reaching 1B hex,
the cell transfer was interrupted by the link-layer and the
previous bytes of the cell should be dropped. When
w_adr reaches 1B hex, a complete 54-byte cell has been
received. The w_adr will reset to 00 hex and w_enable is
de-asserted until another cell transfer begins. The
w_phy_act signal is not de-asserted unless the link-layer
deselects the CoreU1PHY by asserting u1_tx_en high.
4
v4.0
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